A junction field effect transistor (hereinafter, referred to as junction FET) which controls a channel with using a pn junction as a gate has been known as one of power semiconductor elements. In particular, a junction FET using SiC as a substrate material is excellent in withstand voltage characteristic because SiC has a dielectric breakdown field larger than that of Si, and since the pn junction has a high diffusion potential, a so-called normally-off FET, which can completely deplete a channel even without applying a negative voltage to a gate, can be achieved.
Japanese Patent Application Laid-Open Publications No. 2007-128965 (Patent Document 1) and No. 2011-171421 (Patent Document 2) disclose trench-type junction FETs. In the junction FETs disclosed in these Patent Documents, a trench is formed in an n−-type drift layer epitaxially grown on a SiC substrate and the sidewalls and the bottom surface of the trench are doped with p-type impurities such as Al (aluminum) by using an oblique ion implantation method and a vertical ion implantation method in combination, thereby forming a p-type gate region.
An on-resistance which is one of important characteristics representing the performance of a junction FET can be reduced by increasing an interval between adjacent gate regions. If doing so, however, the source and drain withstand voltages at the time of a reverse bias are decreased. More specifically, the on-resistance and the source and drain withstand voltages have a tradeoff relation with the interval between gate regions as a parameter. Therefore, the control of this parameter is very important for the improvement of the performance of the junction FET.
Mater. Sci, Forum 600-603. 1059 (2009) (Non-Patent Document 1) reports that it is possible to improve the above-described tradeoff relation between the on-resistance and the source and drain withstand voltages by making the impurity concentration profile of the p-type gate region steep. Although the Non-Patent Document 1 does not describe how to make the impurity concentration profile steep, for example, a method in which an oblique ion implantation method is used to dope the sidewalls of the trench with n-type impurities (for example, nitrogen), thereby compensating for the impurity concentration at an end of the p-type gate region may be adopted (see FIG. 3 of Non-Patent Document 1).
Japanese Patent Application Laid-Open Publication No. 10-294471 (Patent Document 3) relates to a planar-type junction FET. The Patent Document 3 describes that the performance of the junction FET can be further improved by making a retrograde profile in which the width of the p-type gate region on a drain side is wider than that on a source side. Here, the width of the p-type gate region is adjusted by ion implantation energy and the dose amount of impurities.
On the other hand, Japanese Patent Application Laid-Open Publication No. 2004-134547 (Patent Document 4) which relates to a trench-type junction FET discloses a method in which the width of the p-type gate region on the drain side is made wider than that on the source side by making the acceleration voltage at the time of ion implantation of impurities to the bottom surface of the trench lower than the acceleration voltage at the time of ion implantation of impurities to the sidewalls of the trench (see FIG. 5 of the Patent Document 4).